The present invention relates to a multi-channel integrated circuit (IC) in which a digital to analogue converter (DAC) is provided in each channel, and in which crosstalk is minimised. The invention also relates to a method for minimising crosstalk between the DACs in the respective channels.
In signal processing ICs for audio, video and data communications, multi-channel processing circuits are required. Each channel is provided with a DAC, and comprises a digital input front end for receiving a digital input signal which is applied to the DAC, and an analogue output end from which an analogue output signal converted from the digital input signal is outputted or further processed. In the processing of audio, video and data signals, and in particular, in the processing of video signals in a multi-channel signal processing circuit, it is essential that the respective channels of the circuit be matched, and in particular, it is important that the analogue end of the DACs of the respective channels should be matched. Mismatch in the analogue ends of the respective DACs can lead to the DACs exhibiting different gain values. Processing effects and minor silicon variations in the die can lead to such mismatch. Various methods and circuitry are provided for minimising mismatch in such DACs, however, in general, such known methods and circuits tend to lead to an increase in crosstalk between the respective DACs. In many applications this is unacceptable.
DACs for use in multi-channel processing circuits for processing audio, video and data communications, in general, are current steering DACs, which comprise a plurality of current sources and associated differential current steering switches. The current steering switches are selectively operable in response to switch bits decoded from a digital word for steering currents from the current sources to either one of a pair of summing nodes for providing an analogue signal corresponding to the digital word. Such current steering DACs may be linear decoded DACs or binary weighted DACs, or may be provided by a combination of both. In a linearly decoded DAC, the DAC current sources are identical to each other, and the differential switches are of identical size. M DAC current sources are provided to convert an N-bit digital word where M is equal to 2Nxe2x88x921. In a binary weighted DAC, the DAC current sources are binary weighted, the current source corresponding to the least significant bit (LSB) providing a current of 20 units, while the current source corresponding to the second least significant bit provides a current of 21 units, and the current source corresponding to the third least significant bit provides a current of 22 units, and so on to the most significant bit, which in an N-bit DAC provides a current of 2Nxe2x88x921 units. The corresponding differential switches are correspondingly binary scaled in size.
The current sources in general are provided by current source devices, typically, MOSFETs coupled to a common supply rail which mirror a reference current provided by a reference circuit. The reference circuit in general comprises a reference current device typically provided by a reference MOSFET coupled to the common supply rail, an amplifier, and a reference resistor. The gates of the current source devices are electrically tied to the gate of the reference FET. The output of the amplifier provides a bias voltage for biasing the gate of the reference current device and the gates of the current source devices. One input of the amplifier is connected to a reference voltage, while the other input is connected to the reference resistor. The reference current device is connected to ground through the reference resistor. The amplifier outputs a voltage which biases the gate of the reference and a reference current is forced through the reference current device and the reference resistor until the voltage across the reference resistor is equal to the reference voltage. The reference current is mirrored in the current source devices. Thus, the value of the reference current, and in turn the gain of the DAC can readily be determined by appropriately selecting the value reference voltage and the resistance value of the reference resistor. In order to facilitate applying a reference voltage to one of the inputs of the amplifier and to facilitate the connection of a reference resistor to the other input of the amplifier and ground, two additional pins are required to the reference circuit.
In order to minimise mismatching, it is known to provide a separate reference circuit for each DAC in a multi-channel signal processing circuit, so that the reference circuits can be located adjacent the corresponding DAC in order to minimise mismatching due to processing effects and silicon variations. However, a disadvantage of providing a separate reference circuit for each DAC is that the die area required for the reference circuits is relatively large in order to accommodate the amplifiers of the respective reference circuits. This is undesirable. Additionally, two extra external pins are required for each reference circuit in order to apply the reference voltages to the amplifiers and in order to connect the respective reference resistors to the amplifiers. Since the trend now is to minimise the number of pins required to an integrated circuit, this is undesirable.
In order to minimise the die area and the number of external pins required by DACs in multi-channel processing circuits, it is known to provide only one reference circuit for all the DACs, and the reference circuit is shared between the DACs. The reference circuit comprises a single amplifier, and the appropriate number of reference current devices are provided connected in parallel between the supply rail and the reference resistor so that one reference current device is provided for each DAC. The respective reference current devices are located as closely as possible to the corresponding DACs. Since only a single amplifier is provided for providing the bias voltage to the reference current devices, the gates of the reference current devices are electrically tied together, thereby causing the gates of the current source devices of all the DACs to be electrically tied together. This results in crosstalk between the respective DACs. The crosstalk results from voltage swings on the current steering switches of one DAC being capacitively fed through to the gates of the current source devices corresponding to the current steering switches of the DAC, thereby modulating the bias voltage on the gates of the current source devices of that DAC. Due to the fact that the gates of the current source devices of the respective DACs are electrically tied together, modulation of the bias voltage on the gates of the current source devices of one DAC appears on the gates of the current source devices of the other DACs, thus causing modulation of the current being steered to the summing nodes of those other DACs, which causes the crosstalk.
In order to minimise the effect of capacitive feedthrough of the voltage swings on the current steering switches to the gates of the corresponding current source devices, it is known to connect an external capacitor between the gates of the current source devices of each DAC and the supply rail, thus minimising crosstalk. However, this requires an external pin to be provided from the gates of the current source devices of each DAC in order to facilitate connection of the respective capacitors during calibration of the respective DACs. This is undesirable, since it increases the pin count of the DACs, and in turn the signal processing circuit, and furthermore does not entirely eliminate crosstalk.
There is therefore a need for a multi-channel circuit comprising DACs in the respective channels of the circuit which overcomes this problem.
The present invention is directed towards providing such a multi-channel circuit, and the invention is also directed towards providing a method for minimising crosstalk between DACs in a multi-channel circuit.
According to the invention there is provided a multi-channel integrated circuit comprising:
a plurality of channels,
a current steering digital to analogue converter (DAC) in each channel,
each DAC comprising a plurality of current sources provided by corresponding current source devices coupled to a common supply rail,
the gates of the current source devices of the DACs being electrically tied together for mirroring a reference current, and being biased by a first bias voltage,
a plurality of current steering switches for steering currents from the current sources to either one of a pair of summing nodes in response to a digital word for providing an analogue output signal on the summing nodes corresponding to the digital word,
a cascode device located between each current source device and the corresponding current steering switch for preventing capacitive feedthrough of voltage swings on the current steering switch to a gate of the corresponding current source device,
a reference circuit for generating the reference current for mirroring by the current source devices of the respective DACs, and for generating the first bias voltage,
a cascode bias voltage circuit being provided for each DAC for providing a second bias voltage for biasing the gates of the cascode devices of the corresponding DAC, the gates of the cascode devices of each DAC being electrically tied to the corresponding cascode bias voltage circuit and being isolated from the gates of the cascode devices of the other DACs for preventing voltage swings on the current steering switches capacitively fed through to the gates of the corresponding cascode devices being transferred to the gates of the cascode devices of the other DACs for minimising crosstalk between the DACs.
Preferably, a reference current circuit is provided for each DAC for generating the reference current for the DAC, each reference current circuit being coupled to the common supply rail, and forming a part of the reference circuit. Advantageously, each reference current circuit comprises a first primary reference current device for generating the reference current for the corresponding DAC, a gate of each first primary reference current device being electrically tied to the gates of the current source devices of the corresponding DAC.
In one embodiment of the invention the reference circuit comprises an amplifier having an output coupled to the gates of the respective first primary reference current devices for providing the first bias voltage thereto, the amplifier having a first input for receiving a reference voltage, and a second input connected to ground through a reference resistor, the respective first primary reference current devices being connected in parallel with each other between the common supply rail and ground through the reference resistor so that respective reference currents are forced through the respective first primary reference current devices as the amplifier maintains the voltage on the second input thereof equal to the reference voltage applied to the first input for establishing the respective reference currents through the first primary reference current devices.
In another embodiment of the invention each reference current circuit comprises a second primary reference current device corresponding to the cascode devices of the corresponding DACs, the second primary reference current device of each reference current circuit being coupled between the first primary reference current device and the reference resistor and in series therewith so that the corresponding reference current flows through the first and second primary reference current devices, a gate of each second primary current device being electrically tied to the gates of the cascode devices of the corresponding DAC.
Preferably, the reference current circuits are similar to each other. Advantageously, each reference current circuit is provided adjacent its corresponding DAC.
In one embodiment of the invention each cascode bias voltage circuit derives the second bias voltage for the gates of the cascode devices of the corresponding DAC from the output voltage of the amplifier of the reference circuit.
In another embodiment of the invention each cascode bias voltage circuit is isolated from the output of the amplifier of the reference circuit by a corresponding secondary current mirror circuit.
In a further embodiment of the invention each secondary current mirror circuit comprises a first secondary reference current device, the gate of which is biased by the output of the amplifier, a second secondary reference current device being connected in series with the first secondary reference current device between the common supply rail and ground, and a third secondary reference current device the gate of which is electrically tied to the second secondary reference current device for mirroring the current through the second secondary reference current device in the third reference current device, the third reference current device being connected in series with a diode connected device between the common supply rail and ground for establishing the second bias voltage between the diode connected device and the third secondary reference current device.
Preferably, the cascode bias voltage circuits are similar to each other. Advantageously, each cascode bias voltage circuit is located adjacent the corresponding DAC.
In one embodiment of the invention the respective current sources of each DAC are binary weighted.
In another embodiment of the invention the current source devices of each DAC are located relatively close to each other.
In a further embodiment of the invention the respective DACs are located relatively close to each other.
Preferably, the reference current circuits are connected to the reference resistor at a common node, and the second input of the amplifier is connected to the common node.
In one embodiment of the invention three external pins are provided to the multi-channel circuit, a first external pin being connected to the first input of the amplifier for applying the reference voltage thereto, a second external pin being provided as a ground pin, and a third external pin being connected to the common node for facilitating connection of the reference resistor between the common node and ground.
The invention also provides a method for minimising crosstalk between current steering DACs of a multi-channel circuit wherein each DAC comprises:
a plurality of current sources provided by corresponding current source devices, the gates of the current source devices being biased by a first bias voltage,
a plurality of current steering switches for steering currents from the current sources to either one of a pair of summing nodes in response to a digital word for providing an analogue output signal on the summing nodes corresponding to the digital word,
the method comprising the steps of:
coupling a cascode device between each current source device and the corresponding current steering switch for preventing capacitive feedthrough of voltage swings on the current steering switches to a gate of the corresponding current source device, and
biasing the gates of the cascode devices of each DAC with respective second bias voltages so that the gates of the cascode devices of each DAC are isolated from the gates of the cascode devices of the other DACs.
The advantages of the invention are many. A particularly important advantage of the invention is that crosstalk between the respective DACs is minimised. This is achieved by virtue of the fact that the cascode devices are provided between the current source devices and the corresponding current steering switches, and in particular, by virtue of the fact that the gates of the cascode devices of each DAC are electrically isolated from the gates of the cascode devices of the other DACs. The cascode devices prevent voltage swings on the current steering switches being capacitively fed through to the gates of the current source devices, and while voltage swings on the current steering switches may be capacitively fed through to the gates of the corresponding cascode devices, since the gates of the cascode devices of each DAC are electrically isolated from the gates of the cascode devices of the other DACs, modulation of the bias voltage on the gates of the cascode devices of one DAC has no effect on the bias voltage on the gates of the cascode devices of the other DACs, thus effectively eliminating crosstalk between the respective DACs. The provision of a separate cascode bias voltage circuit for each DAC permits the gates of the cascode devices to be isolated from each other. Additionally, by virtue of the fact that the cascode devices prevent capacitive feedthrough of current swings on the respective current steering switches to the gates of the current source devices, the bias voltage on the gates of the current source devices of each DAC is constant since the output voltage of the amplifier of the reference circuit remains constant. Modulation of the voltage on the gate of one cascode device due to a voltage swing on the corresponding current steering switch has less effect on the currents flowing through the other cascode devices of the corresponding DAC than would be caused by modulation on the gate of one of the current source devices, since the voltage tolerance permitted on the gates of the cascode device is considerably broader than the voltage tolerance which is permitted on the current source devices, since it is the current source devices which set the respective currents for the DACs.
Additionally, by virtue of the fact that the respective DACs share the reference circuit, and in particular, by virtue of the fact that the reference circuit comprises a plurality of reference current circuits, one reference current circuit being provided for each DAC, the reference current circuits of the respective DACs may be located adjacent the DACs, and thus mismatching, and in particular, gain mismatching between the respective DACs is minimised while at the same time avoiding crosstalk.
A further advantage of the invention is that crosstalk is minimised and effectively eliminated without the need for an external capacitor connected between the gates of the current source devices of each DAC and the voltage supply rail.
Another advantage of the invention is that the insertion of the cascode devices between the current source devices and the corresponding current steering switches of the respective DACs increases the effective impedance of the current sources, and thus increases the output impedance of the respective DACs.
The invention will be more clearly understood from the following description of a preferred embodiment thereof, which is given by way of example only, with reference to the accompanying drawings.